module compile_time_test_top(
	input	wire						local_clk_50mhz	
);



localparam  FPGA_CODE_VERSION  =   "FPGA_CODE_VERSION 1.0.00.xxxx001"; // 注意长度应该为32个字节(256bit)

wire			clk_100mhz;
pll_system_clock pll_system_clock_inst(
	.refclk		(local_clk_50mhz	),   //  refclk.clk
	.rst		(1'b0				),      //   reset.reset
	.outclk_0	(clk_100mhz			), // outclk0.clk
	.locked		(locked				)    //  locked.export
);


wire			reset_n;
assign reset_n = locked;



fpga_version #(
    .FPGA_CODE_VERSION(FPGA_CODE_VERSION)
) fpga_version(
    .clk    (clk_100mhz     ),
    .reset_n(reset_n        )
);


endmodule